1. Field of the Invention
The present invention generally relates to field effect transistor structures and, more particularly, to ultra-short channel MOSFET structures.
2. Description of the Prior Art
Transistor designs can be generally grouped into two classes: bipolar transistors and field effect transistors. Bipolar transistors have been developed to very high performance levels and extremely small size in terms of substrate area occupied since the junctions thereof can be formed in sequence in a direction perpendicular to the substrate. However, the basic principles underlying the bipolar transistor require a base or input current when the transistor is in the "on" or conductive state. Also, because conductance occurs across semiconductor junctions, development of bias voltages is required for proper operation.
In contrast, conduction in field effect transistors (FETs) occurs through a channel which need not necessarily contain a junction although junctions have been added to some FET designs to improve performance. The width of the channel and, hence, the resistance of the channel is controlled by a gate which is insulated from the conduction path. Therefore, no continuous current is required for control of the FET but only a small current sufficient to charge and discharge the capacitance of the gate when the conduction state is changed.
Field effect transistors are, therefore, particularly advantageous for logic circuits. The fact that no current is required to maintain conduction increases "fan out" the number of devices that can be reliably driven by a preceding or input device in the overall circuit. Also, since input current is required only during the change of state of the transistor, power consumption and the requirements for heat dissipation are generally low and mostly dependent on the maximum required switching rate and current and resistance in the conduction channel. Further, when logic circuits are developed using field effect transistors, heat dissipation due to the small resistance of the channel is limited by the relatively small currents required when fan out (e,g, the number of devices driven) is suitably limited.
However, since field effect transistors are highly suited to logic circuitry, incentives for miniaturization exist to an even greater extent for field effect transistors than for bipolar transistors. More specifically, the current required during change of conductance states is a function of the gate capacitance. Therefore the speed of response, power consumption (and heat dissipation) and the current requirements (and fan out) are dependent on gate capacitance which may be reduced with the size of the gate or the drain to source channel length. Also, in integrated logic circuits, speed is increased by short conductor length and it is, therefore, very desirable to form as many elements on the same chip as possible.
So-called complementary metal-oxide-semiconductor (CMOS) designs have become popular in logic circuit designs for numerous reasons due to their noise immunity, operability over wide voltage ranges and other properties even though a greater number of transistors is necessary on a chip for equivalent logic functions than with other FET technologies. An impurity well of opposite conductivity type is also required for one of the transistors of each complementary circuit. These additional structures occupy space on the chip and thus further contribute to the incentive for miniaturization of the transistors formed thereon.
Several limitations on miniaturization of field effect transistors have been encountered. Most importantly, perhaps, it is extremely difficult to form field effect transistors with the conduction path or channel other than parallel to the substrate. Therefore, the size of the transistor cannot generally be made smaller than the size of the gate or the conduction channel. Further, as the conduction channel is made small, several adverse effects on transistor performance occur.
Specifically, the series resistance of an FET is a function of both the cross-sectional area and length of the conduction channel. It is desirable to limit the depth to which the conduction channel extends in order to limit the voltage which is needed to control the FET as well as to limit leakage and punch-through effects. This depth is generally limited by the depth to which source and drain contacts extend into a body of semiconductor material such as a structure having shallow impurity implants of an opposite conductivity type to that of the conduction channel material. When such implants extend less than 1500 Angstroms into the conduction channel material, they are commonly referred to as a shallow junction. The use of shallow junctions causes the series resistance to increase. Series resistance must, however, be maintained at a low value in order not to degrade the extrinsic transconductance of FET. In general, the greater the extrinsic transconductance of the FET, the faster the circuit performance obtained. Low series resistance is often achieved by siliciding (i.e. forming a metal silicide at a metal-silicon interface) of the source and drain or selectively depositing metal such as tungsten on the source and drain areas. However, this is difficult to achieve consistently for shallow junctions. The silicidation consumes surface silicon and can give rise to increased leakage current. These increases in series resistance due to the reduction of cross-sectional area of the conduction channel cannot be fully compensated by decreases in the length of the conduction channel. While short conduction channel length is desirable both for miniaturization as well as low series resistance, when the conduction channel length is reduced below about 0.25 .mu.m, threshold voltage (the voltage at which the drain current starts to increase quickly) is reduced due to charge sharing with the drain junction. Similarly, leakage and punch through effects are increased. The leakage or "off" state current is increased due to the reduced threshold voltage, resulting in increased standby current for the chip. When the threshold voltage is lowered by a large amount, the device is said to be "punched through. While the threshold reduction can be limited by reducing the depth of the conduction channel, reduction of depth of the channel degrades series resistance, as discussed above.
The performance of FETs is improved by operating at low temperatures where the increase in carrier (electron or hole) mobility causes transconductance to increase. However, in the prior art, FETs for low temperature applications has simply scaled threshold voltages and oxide thicknesses from "room temperature" designs. Therefore, it is seen that related and conflicting design concerns effectively limit the minimum size at which FETs can be formed without degradation of performance. To date, all efforts to reduce series resistance and short channel effects have required additional regions to be formed, such as Schottky barriers, so-called lightly doped drain structures and the like which increase the number of process steps and have a substantial potential for reducing manufacturing yield due to the stringent requirements for mask registration at extremely small feature sizes.